1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) as a nonvolatile memory using the tunneling magneto-resistive effect and a test method therefor and, more particularly, to a magnetic random access memory having a test circuit (internal test circuit) and a test method therefor.
2. Description of the Related Art
In semiconductor memories such as magnetic random access memories (MRAMs) including both single memories and embedded memories, it is very important to have, as a peripheral circuit, an internal test circuit capable of automatically discriminating a defective bit whose characteristic falls outside the standards of the memory cell characteristic and discriminating a defective chip in the early stages. This is because the test time at the time of test process in mass production can be shortened, i.e., the manufacturing cost can be kept low.
Jpn. Pat. Appln. KOKAI Publication No. 2001-273799 already proposes a resistor type test circuit which determines short and open in the memory cell array portion of an MRAM and also whether the resistance value of each magnetic tunneling junction (MTJ) element that forms a memory cell has a predetermined upper limit value or lower limit value.
It is also known, as the write characteristics of an MTJ element, that there are a shift to “1” data side by Neel coupling and a shift to “0” data side by a stray field.
More specifically, assume that an MTJ element has a desired resistance value. The write characteristics of the MTJ element that constitutes a memory cell is taken into consideration. If the asteroid characteristic of an MTJ element shifts to one of the axes of easy magnetization, a write error may be caused in a half-selected state (or semi-selected state), i.e., by a current for only one of the axis of easy magnetization (or easy axis) and the axis of hard magnetization (or hard axis).
For example, assume that when most memory cells (MTJ elements) in a memory cell array exhibit the asteroid characteristic as shown in FIG. 1A, a memory cell that exhibits the asteroid characteristic as shown in FIG. 1B exists. In a write mode to a normal memory cell, write currents are supplied to the bit and word lines such that a current magnetic field is generated at an intersection N1 between +Ia and +Ib or an intersection N2 between −Ia and +Ib. At this time, if a bit having the asteroid characteristic shown in FIG. 1B is present on the same word line as that of the bit that should be write-accessed, “1” data is erroneously written in the bit. Alternatively, the switching current for a write for one axis Ieasy is defined as +Ic. If a bit with “+Ic<+Ia” is present on the same bit line as that of the bit that should be write-accessed, “1” data is undesirably written in the bit. Referring to FIGS. 1A and 1B, Ieasy and Ihard indicate currents necessary for generating current magnetic fields along the axes of easy magnetization and hard magnetization for an MTJ element that forms a memory cell.
As described above, assume that, in an MRAM which executes a two-axis write, different current values are necessary for generating magnetic fields along the axis of easy magnetization in writing “0” data and “1” data. That is, assume that the write characteristics shift. In this case, data write may be impossible for the bit. Alternatively, the memory cell may become weak against disturbance in the half-selected state. The disturbance means data changes in memory cells to which two-axis current magnetic fields are not applied. To increase the reliability of a memory, a bit having a shift in write characteristics must be excluded as a defective bit.
Examples of categories of defective bits in an MRAM are short of an MTJ element, a memory cell having a resistance value that falls outside the standards due to a failure in a tunnel insulating film, and an inappropriate write characteristics when a write mode is taken into consideration.
A bit whose resistance value of the MTJ element falls outside the standards or a bit having a shift in write characteristics should be determined as a defective bit in mass production. To do this, for example, a checker pattern is written in each memory cell to determine whether the data is “1” or “0”.
However, when, e.g., only the write time is taken into consideration, it is required to ensure a write time of Tw×2 m×2 n where Tw is the write time per bit, m is the number of columns, and n is the number of rows.
When the test process in mass production is taken into consideration, defective bits are preferably detected in the early stages. If a defective bit cannot be replaced with a redundant cell, the chip must be excluded as defective.